The technology disclosed herein relates to semiconductor devices and electronic equipment using the same.
Semiconductor devices used in various types of electronic equipment generally have a configuration including: a semiconductor substrate; an impurity diffusion layer formed in an upper portion of the semiconductor substrate near one of its principal planes (top surface); and a through electrode filled in a through hole extending from one principal plane of the semiconductor substrate through the other principal plane thereof (bottom surface). In a portion near the top surface of the semiconductor substrate, formed are a low-resistance first diffusion layer containing impurities at high concentration and a second diffusion layer containing impurities at low concentration surrounding the first diffusion layer to isolate the first diffusion layer from the semiconductor substrate. The through electrode, having a conductor formed in the through hole, is electrically connected to a connection electrode formed on the top surface of the semiconductor substrate. The through electrode is also electrically connected to an external connection terminal formed on the bottom surface of the semiconductor substrate. An insulating film is formed on the wall of the through hole to cover the side surface of the through electrode (see Japanese Patent Publication No. P2006-41450, for example).